发明名称 ANALOG DELAY LOCKED LOOP CAPABLE OF PREVENTING UNLOCKING, ESPECIALLY INCLUDING A VOLTAGE CONTROLLED DELAY LINE AND A LOCKING CONTROLLER FOR CONTROLLING A CHARGE PUMP
摘要 PURPOSE: An analog delay locked loop capable of preventing an unlocking is provided to prevent the unlocking in the analog delay locked loop. CONSTITUTION: An analog delay locked loop capable of preventing an unlocking includes a phase comparator(100), a charge pump(300), a voltage controlled delay line(400), a sensing unit(600) and a locking controller(200). The phase comparator compares the phase of the inner clock signal with the reference clock signal. The charge pump supplies the charges in response to the up signal and the down signal. The voltage controlled delay line delays the reference clock signal by the delay time corresponding to the charge amount supplied from the charge pump to output the delayed reference clock signal as an inner clock signal. The sensing unit senses the state of the reference clock signal at the time when the inner clock signal is shifted. And, the locking controller is provided between the phase comparator and the charge pump for transmitting the up signal and the down signal outputted from the phase comparator or controls the charge pump so as to output the inner clock signal with delaying by a predetermined time.
申请公布号 KR20040102282(A) 申请公布日期 2004.12.04
申请号 KR20030033667 申请日期 2003.05.27
申请人 HYNIX SEMICONDUCTOR INC. 发明人 PARK, IN CHEOL
分类号 G11C8/00;(IPC1-7):G11C8/00 主分类号 G11C8/00
代理机构 代理人
主权项
地址