MULTI-BIT INPUT FIR FILTER FOR PERFORMING SIMULTANEOUSLY 1:4 INTERPOLATION FIR FILTER OPERATION FOR MULTI-BIT INPUTS AND QAM MODULATOR USING THE SAME

摘要

PURPOSE: A multi-bit input FIR filter for performing simultaneously a 1:4 interpolation FIR filter operation for multi-bit inputs and a QAM modulator using the same are provided to reduce a hardware size of the QAM modulator by removing a changing process to one bit input FIR filtering structure. CONSTITUTION: First to fourth input registers are used for storing four filter input data in a period of a first clock. A first multiplexer is used for selecting one of four filter input data according to a second clock. An address converter is used for dividing the output data of the first multiplexer into four address data and outputs the address data having the reduced bit number as much as one bit. First to fourth lookup tables include first to fourth memories, respectively. A first pipeline register is used for delaying the outputs of the second to the fourth lookup tables as much as a predetermined clock. Second to fifth multiplexers are used for selecting one of the output of the first lookup table and the output of the first pipeline register according to the first and the second clocks. A second pipeline register is used for delaying the outputs of the second to the fourth multiplexers as much as a predetermined clock.