MODULAR BINARY MULTIPLIER FOR SIGNED AND UNSIGNED OPERANDS OF VARIABLE WIDTH

摘要

PROBLEM TO BE SOLVED: To realize a shorter CPI for multiplication instructions with respect to a design of a binary multiplier to be used together with functions shown in a general processor environment in fields of arithmetic techniques and logic techniques in computer and processor architectures.

SOLUTION: A concept may be split into two parts, the first of which is multiplication hardware itself and is a compact and less than-full sized multiplier which employs Booth or other type of recording methods upon the multiplier to reduce the number of partial products per scan and is implemented in such a manner that a multiplication operation with large operands may be broken into subgroups of operations that will fill into this mid-sized multiplier whose results, here called modular products, may be knitted back together to form a correct final product. The second part of the concept is supporting hardware used to separate the operands into subgroups and to input data and control signals to the multiplier and the algorithm and apparatus used to align and combine the modular products properly to obtain the final product.

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