| 摘要 |
<p>PROBLEM TO BE SOLVED: To delay a rising input without malfunction and to improve the degree of freedom of design. SOLUTION: In C-MOS inverters 1-3 connected in cascade, a gm of a PMOS 1p, an NMOS 2n and a PMOS 3p is selected to be very high so as to allow them to be switched quickly and a gm of an NMOS 1n, a PMOS 2p and an NMOS 3n is selected to be in matching with a desired delay time. The NMOS 1n, PMOS 2p and NMOS 3n are sequentially conductive against a rising input and or usual delay and the PMOS 1p, NMOS 2n and PMOS 3p are quickly conductive against a trailing input, then the output signal is changed in synchronism with the trailing input.</p> |
