发明名称 Integrated circuit testing method, program, storing medium, and apparatus
摘要 An ATPG unit permits allocation of a don't care X as a state for activating a propagating path of a failure and, after a change in network, transfers the state from the don't care X to an uncontrol value, thereby activating the propagating path of the failure. Further, the ATPG unit supplies a system clock as a sending clock to a sending FF, gives a change to the network from the sending FF, propagates the change, supplies the system clock as a receiving clock to a receiving FF, and captures the network change, thereby propagating a state for detecting a delay failure to a path between the sending FF and the receiving FF and generating a test pattern when the propagation succeeds.
申请公布号 US2004243339(A1) 申请公布日期 2004.12.02
申请号 US20040791725 申请日期 2004.03.04
申请人 FUJITSU LIMITED 发明人 MARUYAMA DAISUKE
分类号 G06F11/00;(IPC1-7):G06F11/00 主分类号 G06F11/00
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