| 摘要 |
PROBLEM TO BE SOLVED: To simplify RAW hazard detection and, especially, instruction forwarding while storing the number of pipeline stages currently having not only one flag but also instructions to write the results into specific register file addresses and kinds of each instruction into score board addresses corresponding to specific instructions and also requiring a slightly larger storage space in the score board. SOLUTION: Processor instruction pipelines, which split individual instructions into several sub-stages and thus reduce the complexity of each stage while simultaneously increasing the clock speed, are typical features of RISC architectures. Operands required by the processing are read from a register file. Read-after-write access problems in the pipeline processing can be avoided by using a scoreboard that has an individual entry per address of the register file. Once an instruction enters the pipeline, a flag, indicating the fact that the instruction in the pipeline wants to write its results into each register address, is set at the address of the destination address of this particular instruction. Hence the result is unavailable as long as the flag is set. It is cleared after the instruction process has successfully written the result into the register file. COPYRIGHT: (C)2005,JPO&NCIPI |
