| 摘要 |
There is provided a semiconductor device using an ODT technology, which is capable of minimizing a delay of an RTT formation timing or a misalignment of RTT with respect to clock, which may occur in a conversion of ODT signal before and after a conversion of a power down mode into an active/standby mode. An ODT mode conversion circuit includes: a clock enable control unit for receiving a precharge signal including an information on a presence of a bank access in a semiconductor memory device, detecting whether the semiconductor memory device exits a precharge power down mode or an active power down mode, and outputting a mode classification signal, in which the mode classification signal has different logic levels depending on the precharge power down exit and the active power down exit; an ODT control unit configured to operate in a power down mode or an active/standby mode according to the mode classification signal; and an RTT formation unit for forming an RTT according to an RTT formation control signal that is outputted from the ODT control unit.
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