发明名称 SEMICONDUCTOR MEMORY AND ITS MANUFACTURING METHOD
摘要 <p>PROBLEM TO BE SOLVED: To make securable a sufficient memory cell store node potential and widen operation margin with a low voltage by providing a plurality of boosting capacitors, boosting a plurality of number of times in one cycle, suppressing reduction of the level of a word line caused by leak to the minimum. SOLUTION: Signals WEP, ATD, DTD, and APD are inputted to a four input NOR 12, its outputϕ4 is outputted as a capacitor pre-charge signalϕ5 for boosting from a two input NOR 12 through an inverter 14. On the other hand, the output of a NAND 18 is outputted as boosting capacitor driving signalϕ6 through an inverter 20, and drives an capacitor 26 for boosting. Also, the outputϕ4 is inputted to a three input NOR 25 through an inverter 21, while inputted to the other terminal of the three input NOR 25 through delay inverters 22, 23. An output of the three input NOR 25 is a boosting driving signalϕ7 driving a capacitor 27 for boosting.</p>
申请公布号 JP2000285680(A) 申请公布日期 2000.10.13
申请号 JP19990094065 申请日期 1999.03.31
申请人 SEIKO EPSON CORP 发明人 MIYASHITA KOJI
分类号 G11C11/418;G11C16/02;(IPC1-7):G11C11/418 主分类号 G11C11/418
代理机构 代理人
主权项
地址