发明名称 |
DIVIDER CIRCUIT, SERIAL-PARALLEL CONVERSION CIRCUIT USING THE DIVIDER CIRCUIT AND SERIAL DATA TRANSMITTING AND RECEIVING CIRCUIT |
摘要 |
<p>PROBLEM TO BE SOLVED: To provide a divider circuit which is suitable to divide a reference clock into the one-over-integer value that is not equal to the n-th power of 2 by feeding the output of a logical gate that provides AND between this output and a reset signal back to a data input terminal and outputting the clock obtained by dividing the reference clock into the specific value from an output terminal. SOLUTION: A 2-divider DVD1 divides a reference clock CK into two clocks by feeding the output of an inverter INV5 back to the data input terminal of a flip-flop F/F-5. In other words, the clock CK is once divided into 1/2 by the divider DVD1 and then into 1/n and outputted so that (n-1) pieces of flip- flops and the logical gates are alternately arranged and cascaded together and also the output of a multi-input logical gate using the outputs of those logical gates and a reset signal as inputs is fed back to the input terminal of the F/F-5.</p> |
申请公布号 |
JP2000286695(A) |
申请公布日期 |
2000.10.13 |
申请号 |
JP19990091307 |
申请日期 |
1999.03.31 |
申请人 |
HITACHI LTD |
发明人 |
SUZUKI HIROSHI |
分类号 |
H03K21/00;H03K23/00;H03M9/00;H04L7/027;(IPC1-7):H03K23/00 |
主分类号 |
H03K21/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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