发明名称 Semiconductor damascene trench and methods thereof
摘要 A memory device cell layout, a computer system comprising a memory device having a particular cell layout, and methods of fabricating static memory cells and semiconductor devices embodying the cells are also provided. In accordance with one embodiment of the present invention, a memory device cell layout is provided comprising four active areas positioned between selected ones of the gates and local interconnects associated with different damascene trenches of the device.
申请公布号 US2004241945(A1) 申请公布日期 2004.12.02
申请号 US20040883522 申请日期 2004.07.01
申请人 发明人 ABBOTT TODD R.
分类号 H01L21/762;H01L21/768;H01L21/8234;H01L21/8244;H01L27/11;(IPC1-7):H01L21/823;H01L21/476;H01L29/76 主分类号 H01L21/762
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