发明名称 POWER CONSUMPTION CALCULATION DEVICE
摘要 PROBLEM TO BE SOLVED: To obtain a power consumption calculation device having high power consumption estimation accuracy, shortening the processing time of logical simulation, and reducing the load of a processor, as to a power consumption calculation device having a logical simulation function. SOLUTION: The power consumption calculation device is provided with: a means for generating extraction target information to be an extraction target of signal change probability information based on logical simulation; a means for extracting the signal change probability information to be the extraction target by executing the logical simulation on the basis of the extraction target information; a means for calculating the signal change probability information of terminals other the extraction target and that of a network; a means for storing power consumption information corresponding to the signal changes of the terminals in a semiconductor integrated circuit and the network; and a means for calculating the power consumption of each logical gate on the basis of the signal change probability information and the power consumption information, and calculating the power consumption of a semiconductor integrated circuit. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2004341952(A) 申请公布日期 2004.12.02
申请号 JP20030139402 申请日期 2003.05.16
申请人 RENESAS TECHNOLOGY CORP 发明人 UCHIMURA YOJIRO
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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