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发明名称
堆叠式半导体封装
摘要
一种堆叠式半导体封装,包括两个半导体晶片(11、12),其中每一晶片具有一架设表面以于一预定之图案中提供复数个晶片引脚设置。该半导体晶片架设于对应之基板表面(13),以使该架设表面与该基板相互对应。该基板上提供了复数个封装引脚于一晶片架设之外的区域,并以完全相同之预定图案配置该封装引脚。该对应于晶片引脚之两半导体晶片连接至中间位置之介层孔,以形成彼此长度相同之分支金属线。该介层孔藉由共用金属线连接至封装引脚,其中该封装引脚对应于连接至介层孔之该晶片引脚。
申请公布号
TW200427012
申请公布日期
2004.12.01
申请号
TW093105058
申请日期
2004.02.27
申请人
尔必达存储器股份有限公司
发明人
菊地涉;管野利夫;伊佐聪
分类号
H01L23/12
主分类号
H01L23/12
代理机构
代理人
洪澄文
主权项
地址
日本
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