发明名称 |
Phase locked loop with control voltage centering |
摘要 |
A phase-locked loop (PLL) with reduced jitter is provided. The PLL includes dual path voltage-controlled oscillator inputs, with a control voltage from a loop filter sent through a low gain path and an integrated error voltage sent through a high gain path. The error voltage is derived from the difference between a reference value representing averaged control voltage and a predetermined portion of the control voltage.
|
申请公布号 |
US6826246(B1) |
申请公布日期 |
2004.11.30 |
申请号 |
US19990418652 |
申请日期 |
1999.10.15 |
申请人 |
AGERE SYSTEMS, INC. |
发明人 |
BROWN JAMES E. C.;SONNTAG JEFFREY LEE |
分类号 |
H03L7/093;H03L7/107;H03L7/18;(IPC1-7):H03D3/24 |
主分类号 |
H03L7/093 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|