发明名称 Semiconductor memory having multiple redundant columns with offset segmentation boundaries
摘要 A memory device with a segmented column architecture that allows for single bank repair across any two row blocks is disclosed. Multiple redundant columns are provided that have offset segment boundaries, i.e., a first redundant column is divided into four segments consisting of row block <0,1>, row block <2,3>, row block <4,5> and row block <6,7>, and a second redundant column is divided into four segments consisting of row block <1,2>, row block <3,4>, row block <5,6> and row block <0,7>. By offsetting the segment boundaries, the repair of the memory device can be optimized by repairing any two adjacent row blocks with only one column segment by selecting the appropriate redundant column segment.
申请公布号 US6826098(B2) 申请公布日期 2004.11.30
申请号 US20030435590 申请日期 2003.05.12
申请人 MICRON TECHNOLOGY, INC. 发明人 BLODGETT GREG A.
分类号 G11C8/12;G11C29/00;(IPC1-7):G11C7/00 主分类号 G11C8/12
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