| 摘要 |
PROBLEM TO BE SOLVED: To prevent electric short circuit due to remaining of polycrystalline silicon and increase of parasitic capacity of a gate electrode and to suppress inverse narrow channel effect in SOI (Silicon On Insulator)-MIS (Metal Insulator Semiconductor) FET. SOLUTION: A gate insulating film 14, a first polycrystalline silicon film 15 and a stopper nitride film (16) are sequentially deposited on a SOI substrate having a silicon film 13. Sides of the silicon film 13 and the first polycrystalline silicon film 15 are etched and element isolation trenches are formed so that inverse tapered shape faces (taper angleθis obtuse angle) are formed. An STI embedding insulating film 17 is deposited and is flattened by CMP. The stopper nitride film (16) and the insulating film 17 are etched by RIE of uniform velocity and a flat surface is obtained. A second polycrystalline silicon film 18 is deposited on it (e), and the laminated polycrystalline silicon film is etched so as to form laminated gate electrodes (15 and 18) (f). Then, a source/drain region 21, a silicide film 22, an interlayer insulating film 23 and metal wiring 24 are formed (g). COPYRIGHT: (C)2005,JPO&NCIPI
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