发明名称
摘要 PURPOSE: A network address translator is provided to simplify the configuration of circuit and reduce manufacturing costs by integrating memories of the host processor and switch. CONSTITUTION: A network address translator comprises a system bus(10) for transmission of data; a host processor(12) for executing a software for translating network addresses; a WAN(wide area network) MAC(media access controller)(14) for transmitting data through the shared WAN transmission path; a switch(16) serving as a master, and which is connected to the system bus and switches Ethernet packet; a system bus arbiter(18) connected to the host processor, WAN MAC and the switch, and which determines system bus use priority of each unit; a system memory(20) serving as a slave, and which is connected to the system bus, integrates the data related to the software of the host processor and the packet passing through the switch, and stores the integrated data and packet; and a memory controller(22) for controlling the system memory.
申请公布号 KR100458289(B1) 申请公布日期 2004.11.26
申请号 KR20020071489 申请日期 2002.11.18
申请人 发明人
分类号 H04L12/28 主分类号 H04L12/28
代理机构 代理人
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