| 发明名称 |
TRI-LAYER MASKING ARCHITECTURE FOR PATTERNING DUAL DAMASCENE INTERCONNECTS |
| 摘要 |
<p>This invention relates to a method of dual damascene integration for manufacture of integrating circuits using three top hard mask layers having alternating etch selectivity characteristics.</p> |
| 申请公布号 |
KR20040099390(A) |
申请公布日期 |
2004.11.26 |
| 申请号 |
KR20047015692 |
申请日期 |
2003.03.28 |
| 申请人 |
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发明人 |
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| 分类号 |
H01L21/3065;H01L21/3205;H01L21/027;H01L21/033;H01L21/28;H01L21/311;H01L21/312;H01L21/316;H01L21/4763;H01L21/768 |
主分类号 |
H01L21/3065 |
| 代理机构 |
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代理人 |
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