| 摘要 |
<p>The device has a master delay locked loop (MDLL) for producing equidistant reference phase signals, a slave delay locked loop (SDLL) with serial connected slave delay units , each with a slave delay element, and an analog amplifier that amplifies the delayed element output signal by a weighting coefficient to generate a weighted delay signal and a subtraction device for subtracting the weighted delayed signal selected by a multiplexer from the received data signal to generate a distortion corrected output data signal. An independent claim is also included for the following: (a) a method of distortion correction of a received data signal.</p> |
