Memory integrated circuit including an error detection mechanism for detecting errors in address and control signals

摘要

A memory integrated circuit including an error detection mechanism for detecting errors in address and control signals. The memory integrated circuit includes a memory array including a plurality of memory cells configured to store data. The memory integrated circuit also includes an address logic unit coupled to the memory array which may be configured to receive a plurality of memory requests each including address information and corresponding error detection information. The corresponding error detection information may be dependent upon the address information. The memory integrated circuit further includes error detection logic which is coupled to the address logic and may be configured to detect an error in the address information based upon the corresponding error detection information and may provide an error indication in response to detecting the error.