发明名称 |
Processor system having java accelerator |
摘要 |
In a processor system comprising of a processor having an instruction decoder 22, a general register 61 composed of a plurality of register areas and at least one ALU 60, and a Java accelerator 30 for converting a Java bytecode sequence to a native instruction sequence for the processor and supplying the native instruction sequence to the instruction decoder. The Java accelerator 30 is composed of a bytecode translator 40 for converting the Java bytecode sequence to the native instruction sequence for the processor and a register status control unit 50 for mapping a Java operand stack to any of the register areas of the general register and detecting a bytecode redundant for the processor. When a redundant bytecode is detected by the register status control unit 50, the supply of the native instruction from the bytecode translator 40 to the instruction decoder 22 is inhibited.
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申请公布号 |
US2004236927(A1) |
申请公布日期 |
2004.11.25 |
申请号 |
US20040488537 |
申请日期 |
2004.03.04 |
申请人 |
IRIE NAOHIKO;ARAKAWA FUMIO |
发明人 |
IRIE NAOHIKO;ARAKAWA FUMIO |
分类号 |
G06F9/30;G06F9/318;G06F9/38;G06F9/45;(IPC1-7):G06F9/30 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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