发明名称 |
Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor |
摘要 |
A memory cell for a memory array in a folded bit line configuration. The memory cell includes an access transistor formed in a pillar of single crystal semiconductor material. The access transistor has first and second source/drain regions and a body region that are vertically aligned. The access transistor further includes a gate coupled to a wordline disposed adjacent to the body region. The memory cell also includes a passing wordline that is separated from the gate by an insulator for coupling to other memory cells adjacent to the memory cell. The memory cell also includes a trench capacitor. The trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor. The trench capacitor also includes a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide.
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申请公布号 |
US2004235243(A1) |
申请公布日期 |
2004.11.25 |
申请号 |
US20040879378 |
申请日期 |
2004.06.29 |
申请人 |
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发明人 |
NOBLE WENDELL P.;FORBES LEONARD |
分类号 |
H01L21/8242;H01L27/108;(IPC1-7):H01L21/824;G11C7/02 |
主分类号 |
H01L21/8242 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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