METHOD AND CIRCUIT FOR THE DETECTION OF SOLDER-JOINT FAILURES IN A DIGITAL ELECTRONIC PACKAGE

摘要

The solder-joint integrity of digital electronic packages, such as FPGAs (120) or microcontrollers that have internally connected input /output buffers (146a/b, 148a/b), is evaluated by applying a time-varying voltage through one or more solder- joint networks (153a) to charge a charge- storage component (156). Each network includes an I/O buffer (146a) on the die (138) in the package and a solder-joint connection (124), typically one or more such connections inside the package and between the package and a board. The time constant for charging the component is proportional to the resistance of the solder- joint network, hence the voltage measured across the charge-storage component is an indicator of the integrity of the solder-joint network.