| 摘要 |
Efficiently utilizing bandwidth by reading a first subset of a cache line in one clock cycle range, while reading a second subset of the cache line in a second clock cycle range For example, the cache line is "split" into two equal parts, a first part of the cache line is read in a first clock cycle range, while the second part is read in the second clock cycle range. Alternatively, reordering the read or write transactions to efficiently utilize bandwidth on the data bus
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