METHOD FOR INTEGRATION OF SINGLE AND DUAL GATE LOGIC INTO ONE MASK SET

摘要

The present invention relates to a method for fabrication of semiconductor devices providing a predetermined number of at least one particular function, each constituted by an elementary integrated circuitry. A plurality of said elementary integrated circuitries are arranged on a wafer by a usual semiconductor process, such that groups with a predetermined number of said elementary integrated circuitries, which will be incorporated within one of said final semiconductor devices, can be determined in a back-end step of the semiconductor production process. In one of the last production steps electrical connections are made between said elementary integrated circuitries within each of said groups by a semiconductor process step. The final wafer is diced into dies, where each die contains one of said groups of said elementary integrated circuitries. Thus, the wafer can be seen as a chocolate bar, which can be broken into small chunks and bigger chunks, which are defined by the predetermined breaking lines of the chocolate bar. In this metaphor a small chocolate chunk corresponds to a die containing one elementary integrated circuitry and a bigger chunk corresponds to a die containing a group of elementary integrated circuitries, which are electrically connected. Therefore, this method has been named chocolate method.