发明名称 |
Semiconductor device and method for manufacturing the same |
摘要 |
A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs. |
申请公布号 |
US2004232497(A1) |
申请公布日期 |
2004.11.25 |
申请号 |
US20040488401 |
申请日期 |
2004.06.24 |
申请人 |
AKIYAMA SATORU;WATANABE TAKAO;MATSUI YUICHI;HIRATANI MASAHIKO |
发明人 |
AKIYAMA SATORU;WATANABE TAKAO;MATSUI YUICHI;HIRATANI MASAHIKO |
分类号 |
H01L21/8239;H01L21/8242;H01L23/522;H01L27/10;H01L27/105;H01L27/108;H01L27/115;(IPC1-7):H01L29/76 |
主分类号 |
H01L21/8239 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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