发明名称 OUTPUT BUFFER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide an output buffer circuit having a proper compatibility for driving capability between turn-on and turn-off of emphasis processing. SOLUTION: A pre-emphasis output circuit 11 turns on or off emphasis processing to conduct waveform shaping for data d1. Level comparison circuits 12 and 13 compare a signal level of a bit signal S2 during turn-on of emphasis processing and a signal level of the signal during turn-off with reference voltages V1 and V2, respectively. A determining unit 14 distinguishes level difference in signal levels of the bit signal S2 during turn-on and turn-off of emphasis processing based on the comparison result by the level comparison circuits 12 and 13. If both of signal levels do not coincide with, the determining unit 14 sets up a signal level of control signals S4 and S5 to values, by which they coincide with. The determining unit 14 outputs the signal level of the control signals S4 and S5 to the pre-emphasis output circuit 11 to control driving capability of the pre-emphasis output circuit 11. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2004336407(A) 申请公布日期 2004.11.25
申请号 JP20030129854 申请日期 2003.05.08
申请人 NEC CORP 发明人 FUKUMA YASUAKI
分类号 H03K19/0175;H04L25/02;(IPC1-7):H03K19/017 主分类号 H03K19/0175
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