发明名称 CONTROLLER INTERFACE
摘要 <p>An interface includes a slave digital signal processor (DSP) and a master DSP connected to the slave DSP through a communications port. The master DSP includes a memory; and a direct memory access (DMA) to the memory. A field programmable gate array (FPGA) is connected to the master DSP. The FPGA includes a dual port random access memory (RAM) in communication with the DMA. A universal serial bus (USB) interface is connected to the FPGA through the dual port RAM.</p>
申请公布号 WO2004102411(A1) 申请公布日期 2004.11.25
申请号 WO2004US13583 申请日期 2004.05.03
申请人 LING DYNAMIC SYSTEMS, INC.;ZHUGE, JAMES;TANG, ZHENGGE 发明人 ZHUGE, JAMES;TANG, ZHENGGE
分类号 G06F3/00;G06F13/00;G06F13/38;G06F15/17;G06F15/78;G06F17/00;(IPC1-7):G06F15/17 主分类号 G06F3/00
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