Photo mask for fabricating semiconductor device having dual damascene structure

摘要

A photo mask for fabricating a semiconductor device having a dual damascene structure which has a via coupled with a lower wiring layer and has an upper wiring layer coupled with the via. The via and the upper wiring layer are fabricated by filling a via hole and a wiring groove formed in an interlayer insulating film that is formed on the lower wiring layer with a wiring material. The photo mask has a via alignment mark which is used for aligning the via hole with respect to the lower wiring layer and/or a via alignment mark which is used for aligning the wiring groove with respect to the via hole. The width of the via alignment mark is equal to or larger than the width which is optically detectable and an aspect ratio of the via alignment mark is equal to or larger than one fourth of the aspect ratio of the via hole. Preferably, the width of the via alignment mark is equal to or larger than the width of the via hole.