发明名称 |
No resonance mode bang-bang phase detector |
摘要 |
A bang-bang phase detector circuit for use in a delay lock loop is disclosed. The phase detector includes a data signal line, a clock signal line, and a delay cell having an input coupled to the data signal line. The phase detector further includes a first double flip-flop having a data input coupled to the data signal line and a clock input coupled to the clock signal line, and a second double flip-flop having a data input coupled to an output of the delay cell and a clock input coupled to the clock signal line. A NOR circuit has a first input coupled to an output of the first double flip-flop and a second input coupled to an output of the second double flip-flop. The phase detector provides a lag output signal line coupled to an output of the NOR circuit, and a lead output signal line coupled to the output of the second double flip-flop.
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申请公布号 |
US6822483(B1) |
申请公布日期 |
2004.11.23 |
申请号 |
US20020121013 |
申请日期 |
2002.04.09 |
申请人 |
APPLIED MICRO CIRCUITS CORPORATION |
发明人 |
FU WEI;BALARDETA JOSEPH J. |
分类号 |
G01R25/00;(IPC1-7):G01R25/00 |
主分类号 |
G01R25/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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