Displays having processors for image data

摘要

A display performing writing and reading operations in synchronization with different signals using a memory. A PLL (phase locked loop) circuit generates a write clock signal from a horizontal synchronization signal and transmits it to a write controller along with the horizontal synchronization signal. The write controller generates write control signals from the signals supplied by the PLL circuit to control writing of the image data into the memory. An oscillator connected to the input terminal of a read controller generates a clock signal independent of the horizontal synchronization signal for the read controller. The read controller generates read control signals using the signals from the oscillator to output into the memory and a display panel, thereby controlling reading of the image data stored in the memory. The writing and the reading of the image data are performed in synchronization with independent signals to realize stable display.