3D CMOS TRANSISTOR AND MANUFACTURING METHOD AT THE SAME
摘要
A three-dimensional FET(field effect transistor) is provided to enable fabrication of devices of various types and shapes by increasing integration of a device and by using all the sidewalls of a fin. A semiconductor substrate(100) has NMOS and PMOS activation regions. The NMOS activation region includes an n-channel region and a source/drain region separated from the n-channel region. The PMOS activation region includes a p-channel region and a source/drain region separated from the p-channel region. The NMOS and PMOS activation regions are formed on the sidewall of the substrate. Gate electrodes(200,210) as upper portions of the n-channel region and the p-channel region are formed on each sidewall of the semiconductor substrate. Gate insulation layers(300,310) are formed between the gate electrodes and the p- and n- channel regions. The height of the NMOS gate electrode can be different from that of the PMOS gate electrode.
申请公布号
KR100853982(B1)
申请公布日期
2008.08.25
申请号
KR20070020629
申请日期
2007.02.28
申请人
KYUNGPOOK NATIONAL UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION