发明名称 Timing recovery loop with non-integer length
摘要 A timing signal is regenerated from an encoded digital signal having a data clock frequency Rb in a receiver using a predetermined sample rate Fs, wherein the data clock period 1/Rb is not an integer multiple of the predetermined sample period 1/Fs. The method comprises generating an input pulse signal in response to the encoded digital signal. Each of the input pulse signals is accumulated in a predetermined delay element which stores an accumulated value, wherein the predetermined delay element is in a delay loop including N delay elements each having a respective accumulated value. The accumulated values are circulated within the delay loop by shifting at each of the sample periods according to a predetermined shift sequence, the predetermined shift sequence including a plurality of single shifts and at least one other shift size to provide a number of shifts N+delta during a cycle of N sample periods. A synchronization pulse is generated in response to the accumulated values and a predetermined threshold. A counter is operated to output the timing signal in response to the predetermined sample rate Fs, the counter having a variable counter period according to a predetermined counter sequence. The variable counter period has an average over time corresponding to the data clock period 1/Rb. The counter is reset in response to the synchronization pulse (if synchronization becomes necessary).
申请公布号 US2004228427(A1) 申请公布日期 2004.11.18
申请号 US20030440497 申请日期 2003.05.16
申请人 WANG YUNG DA;WHIKEHART J. WILLIAM;WHITECAR JOHN ELLIOTT 发明人 WANG YUNG DA;WHIKEHART J. WILLIAM;WHITECAR JOHN ELLIOTT
分类号 H04L27/22;H04H40/45;H04L7/00;H04L7/033;H04L7/04;(IPC1-7):H04L7/00 主分类号 H04L27/22
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