发明名称 |
IMAGE PROCESSING APPARATUS |
摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an image processing apparatus capable of decreasing the capacity of a line memory and carrying out resize processing in units of blocks. <P>SOLUTION: The image processing apparatus is provided with an MPEG decoder 1 for decoding encoded data and outputting image data in units of blocks each having an 8×8 pixel size; a horizontal resize circuit 2 for applying resize processing to the image data outputted from the MPEG decoder in units of blocks in a horizontal direction; the line memory 3 with a capacity of one line for storing image data of a lowermost line of a block among output data from the horizontal resize circuit; a vertical resize circuit 4 for applying resize processing to output data from the horizontal resize circuit and the data stored in the line memory in a vertical direction; a memory controller 5; and a memory 6. The image data after being subjected to the resize processing in the horizontal direction can be stored in the line memory with a small capacity. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
申请公布号 |
JP2004328178(A) |
申请公布日期 |
2004.11.18 |
申请号 |
JP20030117784 |
申请日期 |
2003.04.23 |
申请人 |
OLYMPUS CORP |
发明人 |
TANAKA YOSHINOBU;UENO AKIRA |
分类号 |
G06T3/40;G06K9/32;G06K9/36;H04N1/393;H04N1/41;H04N7/01;H04N7/24;H04N19/00;H04N19/423;H04N19/426;H04N19/59;(IPC1-7):H04N1/41 |
主分类号 |
G06T3/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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