发明名称 LOGIC VERIFICATION PROGRAM AND RECORDING MEDIUM
摘要 PROBLEM TO BE SOLVED: To improve the logic verification efficiency. SOLUTION: The logic verification program allows a personal computer 100 to function as a verification item input editor (S1) which enables an input of a verification item in a natural language on a tabular display screen and to function as a verification result feedback means (S5) which enables the creation of a test report by feeding-back the verification result to the verification item input editor. The processing of the personal computer 100 reduces the time required for creating the test report as compared with the case of manual operation, and also reduces man-made mistakes due to the unnecessity for troublesome manual operations. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2004326650(A) 申请公布日期 2004.11.18
申请号 JP20030123402 申请日期 2003.04.28
申请人 RENESAS TECHNOLOGY CORP 发明人 KAMATA TAKEROO
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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