| 摘要 |
Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory controller for controlling access to a memory module, wherein the memory module has a memory component with a memory core for storing data therein. The memory controller comprises a first set of interface connections for providing access to the memory module, and a second set of interface connections for providing access to the memory module. The memory controller also comprises memory access circuitry for providing memory access signals to the memory module for selecting between a first mode wherein a first portion of the memory core is accessible through the first set of interface connections and a second portion of the memory core is accessible through the second set of interface connections, and a second mode wherein both the first portion and the second portion of the memory core are accessible through the first set of interface connections.
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