| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having self-layout capable of reducing the area, and for securing margin of lithography. <P>SOLUTION: An end part F1 of the gate wiring of a load transistor LO1, projected from an active region PD1, is arranged so as to be oblique with respect to the gate width direction of the load transistor LO1, and an end part F2 of the gate wiring of a load transistor LO2, projected from an active region PD2, is arranged so as to be oblique to the gate width direction of the load transistor LO2. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
