发明名称 Apparatus connectable to a computer network for circuit design verification, computer implemented method for circuit design verification, and computer progam product for controlling a computer system so as to verify circuit designs
摘要 An apparatus for circuit design verification according to an embodiment of the present invention has a verification result collector configured to collect a verification result, a data conversion and registration module configured to convert the verification result to a pre-analysis indication file, an analysis information collector configured to collect analysis information about a redundant non-active portion, an analysis information processor configured to exclude an affect of the redundant non-active portion and make an analysis indication file, an indication file storage portion configured to store the analysis indication file, and a data indication controller configured to output the analysis indication file.
申请公布号 US2004230928(A1) 申请公布日期 2004.11.18
申请号 US20040773702 申请日期 2004.02.06
申请人 NOZUYAMA YASUYUKI 发明人 NOZUYAMA YASUYUKI
分类号 G01R31/317;G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G01R31/317
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