| 摘要 |
A semiconductor memory device is provided to minimize a circuit configuration by supplying a data pattern for a reading operation to an input/output line by a multiplex circuit. A data multiplex part(200) delivers one among a data training pattern and data delivered through a global input/output line in response to a training control signal. A latch(220) latches a value outputted from the data multiplex part, and supplies a latched value to the global input/output line. The data multiplex part includes a first transmission gate, a second transmission gate, and an inverter. The first transmission gate passes the data in response to the training control signal. The second transmission gate passes the data training pattern in response to the training control signal. The inverter inverts the training control signal, and controls the first transmission gate and the second transmission gate by an inverted control signal.
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