发明名称 INFORMATION PROCESSOR AND METHOD FOR MANUFACTURING LSI CHIP
摘要 <p><P>PROBLEM TO BE SOLVED: To evaluate processing result in a process for a short time in a design stage. <P>SOLUTION: According to the hierarchical structure of a circuit function block shown by the wiring design data of an LSI chip, a two-dimensional shape information on wiring or wiring interlayer film included in the circuit function block is acquired from the wiring design data by each of layers corresponding to a photo mask (101), and a layer relating to the two-dimensional shape of wiring or the like to be processed in a process included in a process flow is corresponded to the process (102), and then the setting of dimensional change quantity of the wiring or the like in the process is received (103), and the two-dimensional shape information, a film thickness specified for the process or the like are corrected on the basis of the dimensional change quantity and the corrected data is used to calculate a three-dimensional shape information showing a three-dimensional shape of the wiring or the like (104). The feature variables of the three-dimensional shape shown by the three-dimensional shape information are output corresponding to the dimensional change quantities (105). <P>COPYRIGHT: (C)2005,JPO&NCIPI</p>
申请公布号 JP2004327810(A) 申请公布日期 2004.11.18
申请号 JP20030122022 申请日期 2003.04.25
申请人 RENESAS TECHNOLOGY CORP 发明人 MORISAWA TOSHIHIRO;SAWA SHINJI;ARAI TOSHIYUKI
分类号 G06F19/00;H01L21/02;H01L21/3205;H01L21/768;H01L23/52;H01L23/522;(IPC1-7):H01L21/02;H01L21/320 主分类号 G06F19/00
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