| 摘要 |
PROBLEM TO BE SOLVED: To improve the data processing efficiency and debugging efficiency of an internal processor of a processor element by speeding up the data transfer between processor elements while minimizing the increase in circuit scale. SOLUTION: This multiprocessor system comprises a plurality of processor elements 01-0n for acquiring the bus use right of a first or second shared bus in response to a transfer request of control system data or input/output data, and multiplex-transferring or burst-transferring it as a master. In this system, the processor elements 01-0n output a bus request signal of the first shared bus in response to the transfer request of control system data, and transfer and output, in response to input of a bus permission signal, selection signal, control signal and address signal of transfer destination and the control system data in one cycle as a master. The processor elements further input the control system data as a slave selectively based on the selection signal through the first shared bus, and process them based on the control signal and address signal. COPYRIGHT: (C)2005,JPO&NCIPI |
