发明名称 |
MOS transistor with elevated source/drain structure and method of fabricating the same |
摘要 |
In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.
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申请公布号 |
US2004227164(A1) |
申请公布日期 |
2004.11.18 |
申请号 |
US20040823420 |
申请日期 |
2004.04.13 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LEE SEUNG-HWAN;PARK MOON-HAN;RHEE HWA-SUNG;LEE HO;YOO JAE-YOON |
分类号 |
H01L21/336;H01L29/78;(IPC1-7):H01L29/74 |
主分类号 |
H01L21/336 |
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地址 |
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