发明名称 |
Distributed switch memory architecture |
摘要 |
A distributed memory switch system for transmitting packets from source ports to destination ports, comprising: a plurality of ports including a source port and a destination port wherein a packet is transmitted from the source port to the destination port; a memory pool; and an interconnection stage coupled between the plurality of ports and the memory pool such that the interconnection stage permits a packet to be transmitted from the source port to the destination port via the memory pool.
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申请公布号 |
US2004228340(A1) |
申请公布日期 |
2004.11.18 |
申请号 |
US20030704510 |
申请日期 |
2003.11.06 |
申请人 |
INTEL CORPORATION |
发明人 |
AKELLA VISVESWAR;SHARMA SANJAY;BOMMIREDDY AMALKIRAN;VENKATACHALAM DINESH |
分类号 |
H04L12/56;(IPC1-7):H04L12/50 |
主分类号 |
H04L12/56 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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