| 摘要 |
A memory access system (100) transfers data to and from a shared memory via a pipeline architecture. The granting of a memory access request effects a substantially direct connection between the requesting process and the pipeline. During a write operation, the requesting process (P1-Pn) pipes the data into the pipeline, and is assured that the data will eventually arrive at the target memory (180) in the order in which it was provided to the pipe. During a read operation, the memory (180) pipes the data into the pipeline, and is assured that the appropriate requesting process (P1-Pn) will be connected to the pipe to receive its data at the other end of the pipe. The sequencing of processes onto the pipe is controlled by a flag that is attached to the last element of each data block in the pipe. |
