| 摘要 |
PROBLEM TO BE SOLVED: To reduce a delay of a pulse signal supplied to a processing circuit via wiring. SOLUTION: While a switch SW1 is turned on, the terminal potential of wiring L1 is made higher than a reference voltage V1 by an "H" level input of a clock signal and when an output of a comparator 62 reaches an "H" level, an output of an EXOR circuit 63 reaches the "H" level. Then, a switch SW3 is turned on and the terminal potential of the wiring L1 is backed up by the rising side of the clock signal to rapidly reach the "H" level. An output of a delay circuit 64 reaches the "H" level, an output of an EXOR circuit 65 reaches the "H" level, and a switch SW2 is turned on. In such a state, the terminal potential of the wiring L1 becomes lower than a reference potential V2 by an "L" level input of the clock signal and when the output of the comparator 62 reaches an "L" level, the output of the EXOR circuit 63 reaches the "H" level. Then, the switch SW3 is turned on, and the terminal potential of the wiring L1 is backed up with the falling side of the clock signal to rapidly reach the "L" level. COPYRIGHT: (C)2005,JPO&NCIPI
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