发明名称 MULTI-CPU SYSTEM AND INTERRUPTION CONTROL METHOD FOR THE SYSTEM
摘要 PROBLEM TO BE SOLVED: To speed up processing in a master unit by eliminating a waste time generated in the master unit which cannot acquire the control right of a common bus by a bus adjustment in an interruption response cycle in a multi-CPU system. SOLUTION: A master selection part 302 which detects an interruption signal by an interruption generation part 303 selects a master unit different from the present bus master reported by a bus master detection part 304, and outputs an M1 interruption signal 12 to be inputted only to a master unit M1 or an M2 interruption signal 14 to be inputted only to a master unit M2, thereby reporting the generation of a service request to a master unit which does not acquire the control right of the common bus at the present. The master unit which inputs the interruption signal immediately acquires the control right of the common bus after it is detected that the other master unit abandons the control right of the common bus, and executes the interruption response cycle responding to the interruption from a slave unit on the common bus. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2004326496(A) 申请公布日期 2004.11.18
申请号 JP20030121140 申请日期 2003.04.25
申请人 NEC SAITAMA LTD 发明人 MORITA TETSUYA
分类号 G06F15/177;G06F13/24;(IPC1-7):G06F13/24 主分类号 G06F15/177
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