发明名称 |
Method and apparatus for mirroring units within a processor |
摘要 |
A processor responsive to a clock cycle includes a base-unit, a mirror-unit that is a duplicate instance of the base-unit, a non-duplicate-unit in signal communication with the base and mirror units, a first staging register disposed at the input to the mirror-unit for delaying the input signal thereto by at least one clock cycle, and a second staging register disposed at the output of the mirror-unit for delaying the output signal therefrom by at least one clock cycle. The non-duplicate-unit includes a comparator for comparing the output signals of the base and mirror units.
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申请公布号 |
US2004230856(A1) |
申请公布日期 |
2004.11.18 |
申请号 |
US20030435914 |
申请日期 |
2003.05.12 |
申请人 |
BILLECI MICHAEL;SHUM CHUNG-LUNG K.;SLEGEL TIMOTHY J. |
发明人 |
BILLECI MICHAEL;SHUM CHUNG-LUNG K.;SLEGEL TIMOTHY J. |
分类号 |
G06F1/04;(IPC1-7):G06F1/04 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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