发明名称 STATE MONITORING SYSTEM FOR WATCHDOG TIMER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To correctly notify a failure due to a clock anomaly by preventing an erroneous determination indicating an anomaly in software on a processor according to a watchdog timer alarm, when a clock anomaly causes a malfunction of the processor. SOLUTION: When a watchdog timer circuit 2 operated at a second clock 24 to detect a malfunction of a processor 1 operated at a first clock 22 is timed out, a first clock anomaly detection circuit 5 for detecting an anomaly in the first clock upon the lapse of a predetermined time checks whether a first clock anomaly is detected or not; and if finding a first clock anomaly, outputs a first failure notification signal 21 indicating a malfunctioning state of the processor due to the first clock anomaly, and if finding no first clock anomaly, outputs a second failure notification signal 21 indicating an anomaly in software on the processor 1. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2004326405(A) 申请公布日期 2004.11.18
申请号 JP20030119740 申请日期 2003.04.24
申请人 NEC CORP 发明人 YANAGI SHUZO
分类号 G06F11/30;G06F1/04;(IPC1-7):G06F11/30 主分类号 G06F11/30
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