COMPENSATION CIRCUIT AND INVERTER STAGE FOR OSCILLATOR CIRCUIT

摘要

A circuit includes an oscillator circuit to receive a bias current and generate an oscillating signal at an output node. A current differencing circuit subtracts a current at the output node from a reference current to generate a first current. In addition, a current mirroring circuit mirrors the first current to generate the bias current. An inverter stage is coupled to the output node, and includes an input branch configured to receive the oscillating signal and generate first and second control signals based upon the oscillating signal. At least one amplifying branch receives the first and second control signals and amplifies the first and second control signals. An output branch receives the amplified first and second control signals and generates an amplified version of the oscillating signal based upon the amplified first and second control signals.

主权项

1. An electronic device, comprising:
an oscillator circuit having a motional resistance and a negative resistance, and comprising a crystal coupled to a first transistor; and a compensation circuit coupled to the oscillator circuit and configured to modulate a first current of the first transistor such that a transconductance of the first transistor increases the negative resistance in the oscillator circuit to compensate for the motional resistance in the oscillator circuit; wherein the compensation circuit comprises:
a second transistor having a first conduction terminal coupled to a node, a second conduction terminal coupled to a first reference supply voltage, and a control terminal coupled to the first transistor such that a second current flowing through the second transistor mirrors the first current;a reference transistor having a first conduction terminal coupled to a second reference supply voltage, a second conduction terminal coupled to said node, and a control terminal coupled to receive a bias voltage that biases the reference transistor to generate a reference current applied to said node; anda third transistor having a first conduction terminal coupled to said node, a second conduction terminal coupled to the second reference supply voltage, and a control terminal for controlling generation of said first current, the third transistor configured to carry a third current representing a difference between the reference current and the second current.