MEMORY DEVICE COMMAND DECODING SYSTEM AND MEMORY DEVICE AND PROCESSOR-BASED SYSTEM USING SAME

摘要

Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge of the clock signal, represent a memory command. Furthermore, the signal provided to the memory address node at a second clock edge of the clock signal is not decoded in combination with the received command signals. The memory command may be a reduced power command and/or a no operation command.

主权项

1. A method of operating a memory device, the method comprising:
receiving a first command and first additional information associated therewith, the first command including a first portion and a second portion, the first additional information including a third portion and a fourth portion; and receiving a second command and second additional information associated therewith, the second command including a fifth portion and a sixth portion, the second additional information including a seventh portion and an eighth portion, wherein receiving the first command and the first additional information comprises: receiving the first portion of the first command and the third portion of the first additional information substantially simultaneously with each other at a first timing; receiving the fourth portion of the first additional information at a second timing that is different from the first timing; and receiving the second portion of the first command at one of the first and second timings, wherein receiving the second command and the second additional information comprises: receiving the fifth portion of the second command and the seventh portion of the second additional information substantially simultaneously with each other at a third timing; receiving the eighth portion of the second additional information at a fourth timing that is different from the third timing; and receiving the sixth portion of the second command at one of the third and fourth timings, and wherein the first portion of the first command and the fifth portion of the second command are the same in logic state as each other, and the second portion of the first command and the sixth portion of the second command are different in logic state from each other.