发明名称 Bus architecture techniques employing busses with different complexities
摘要 An integrated circuit system (70) includes a processor (130) and a system bus (12) with a first complexity coupled to the processor. Apparatus for enabling communication between the processor and one or more devices through the system bus include a first device (90), a second device (80), and a first bus interface (72) coupled to the system bus (12), coupled to the first device (90) through a first bus (92) with a second complexity less than the first complexity and coupled to the second device (80) through a second bus (82) with a third complexity less than the first complexity. <IMAGE>
申请公布号 EP1477904(A1) 申请公布日期 2004.11.17
申请号 EP20040009344 申请日期 2004.04.20
申请人 BROADCOM CORPORATION 发明人 SCHONER, BRIAN
分类号 G06F13/14;G06F13/40;(IPC1-7):G06F13/40 主分类号 G06F13/14
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